library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tb_mux_2to1 is
end tb_mux_2to1;

architecture BEH of tb_mux_2to1 is
    component mux_2to1
        Port ( X0 : in  STD_LOGIC_VECTOR(7 downto 0);
               X1 : in  STD_LOGIC_VECTOR(7 downto 0);
               C : in  STD_LOGIC;
               D : out  STD_LOGIC_VECTOR(7 downto 0));
    end component;

    signal X0_tb, X1_tb, D_tb : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
    signal C_tb : STD_LOGIC := '0';

begin
    uut: mux_2to1 port map (
        X0 => X0_tb,
        X1 => X1_tb,
        C => C_tb,
        D => D_tb
    );

    stim_proc: process
    begin
        -- Тестовый сценарий
        X0_tb <= x"01";
        X1_tb <= x"02";
        
        C_tb <= '0';
        wait for 10 ns;
        assert D_tb = x"01" report "Error C=0" severity error;
        
        C_tb <= '1';
        wait for 10 ns;
        assert D_tb = x"02" report "Error C=1" severity error;

        wait;
    end process;
end BEH;